CVE-2026-19571

The ITE IT8xxx2 SHI host-command backend (subsys/mgmt/ec host cmd/backends/ec host cmd backend shi ite.c) copied the 8-byte host-command request header from the SPI Rx FIFO directly into the shared receive buffer data->in msg and only afterwards checked the protocol version and the derived packet length. The interrupt handler also accepted a chip-select assertion and an Rx-valid-length (RVLI) interrupt in any driver state other than SHI STATE DISABLED, so a new header could be parsed while the host-command thread was still processing the previous request out of the very same buffer.

The host processor is the SPI controller and drives both chip select and the clock. After sending a well-formed request it can immediately de-assert chip select — which returns the driver to the ready state and re-enables the FIFO — and start a second transaction carrying a header with data len = 0xFFFF. Those eight bytes are written into in msg before the oversized length is rejected, so they land in a buffer whose contents verify rx() in subsys/mgmt/ec host cmd/ec host cmd handler.c has already validated. If this lands in the window before the host-command thread executes args.input buf size = rx header->data len, the framework hands the registered command handler a 65535-byte input length over a 256-byte buffer.

The result is an out-of-bounds read of up to roughly 64 KiB beyond the request buffer: command handlers that copy or echo input buf size bytes disclose adjacent embedded-controller memory back to the host or overflow the response buffer, and a read past the end of SRAM faults the controller. The same race also allows cmd id and cmd ver to be swapped after checksum verification and after handler lookup. Exploitation requires the ability to drive the inter-processor SHI bus (a compromised host OS or physical access to the SPI lines) and winning a timing race, which the SPI controller can retry indefinitely.

The fix parses the header into a local struct ec host cmd request header and copies it into in msg only after the length has been bounded by sizeof(data->in msg), and ignores chip-select and RVLI interrupts outside SHI STATE READY TO RECV/SHI STATE RECEIVING. A residual, bounded race remains: an end-of-transaction interrupt still resets the state to ready while the host-command thread owns the buffer, so a valid second request can still overwrite the in-flight request's contents, unlike the NPCX backend which parks in SHI STATE CNL RESP NOT RDY while the buffer is in use.