CVE-2026-43191

Name of the Vulnerable Software and Affected Versions Linux kernel (affected versions not specified)

Description An issue exists in the drm/amd/display component where disabling TMDS output turns off the PHY PLL (Phase-Locked Loop), causing the OTG (Output Timing Generator) to remain stuck. This state can lead to a hang in the DCHVM's ability to acknowledge invalidations because it perceives the HUBP as active while not receiving global synchronization. The transition to PLL ON must be atomic to prevent the IOMMU watchdog from timing out if the thread is pre-empted.

Recommendations At the moment, there is no information about a newer version that contains a fix for this vulnerability.