CVE-2025-10263

Name of the Vulnerable Software and Affected Versions Arm C1-Ultra (affected versions not specified) Arm C1-Premium (affected versions not specified) Arm Neoverse V3 & V3AE (affected versions not specified) Arm Neoverse V2 (affected versions not specified) Arm Neoverse V1 (affected versions not specified) Arm Neoverse-N2 (affected versions not specified) Arm Neoverse-N1 (affected versions not specified) Arm Cortex-X925 (affected versions not specified) Arm Cortex-X4 (affected versions not specified) Arm Cortex-X3 (affected versions not specified) Arm Cortex-X2 (affected versions not specified) Arm Cortex-X1 & X1C (affected versions not specified) Arm Cortex-A710 (affected versions not specified) Arm Cortex-A78, A78AE & A78C (affected versions not specified) Arm Cortex-A77 (affected versions not specified) Arm Cortex-A76 & A76A (affected versions not specified) NVIDIA Olympus (affected versions not specified)

Description A privilege escalation issue exists in various Arm CPU cores due to a timing condition during memory permission changes. Specifically, memory access completion is not guaranteed after Translation Lookaside Buffer (TLB) invalidation, which may allow writes to resources owned by a higher exception level. In the context of the Xen hypervisor, this could enable a guest system to write to memory belonging to the hypervisor.

Recommendations Apply the released Linux Kernel patches which implement a software workaround requiring additional TLB invalidation and a synchronization barrier.