CVE-2026-74276

Name of the Vulnerable Software and Affected Versions Linux kernel (affected versions not specified)

Description An issue exists in the Xilinx SPI driver regarding how the FIFO (First-In, First-Out) buffer size is determined. The driver incorrectly calculates the size by writing to the TX FIFO register until the status register asserts full, failing to account for a shift register that can hold an additional byte. This results in an overestimated buffer size (e.g., reporting 17 bytes instead of 16). When operating in irq mode, this discrepancy causes the driver to write more bytes than the RX FIFO can hold, leading to data loss. Subsequently, the driver enters an infinite while loop while checking the status register for the missing byte, which locks the driver. The vulnerable logic is implemented within the xilinx spi rx() function.

Recommendations At the moment, there is no information about a newer version that contains a fix for this vulnerability.