CVE-2026-97587

Name of the Vulnerable Software and Affected Versions Linux kernel (affected versions not specified)

Description An issue exists in the RISC-V architecture implementation of the perf subsystem where the available-counter mask is stored as a single unsigned long. Because the iteration process uses RISCV MAX COUNTERS (64), systems using RV32 (a 32-bit RISC-V architecture) read past the object boundaries. Additionally, filling bits at index 32 and above using an unsigned long is incorrect. This can lead to out-of-bounds reads when checking events, allocating indices, or stopping counters, particularly on platforms like qemu-system-riscv32 where the probe bitmap contains bits above the XLEN (the register width of the architecture).

Recommendations At the moment, there is no information about a newer version that contains a fix for this vulnerability.